[PATCH] D145766: [RISCV] Support Zfa fli instructions with vector splats.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1544
+    // fli.h requires Zfh or Zvfh, but we might only have Zfhmin.
+    if (VT == MVT::f16 &&
+        (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh()) &&
----------------
reames wrote:
> Style: This really should be a switch on VT with a return in each block.
Good point. It worked less well as a switch before I made it its own function.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1550
+      return true;
+    if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1)
+      return true;
----------------
reames wrote:
> Hm, shouldn't this depend on having the D extension?  (follow on)
I'll add an assert. the caller in this file already checks D is enabled. The two calls in RISCVISelDAGToDAG.cpp only occur if f64 is a legal type which would require D if Zfa is enabled. Zfa is incompatible with Zdinx.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145766/new/

https://reviews.llvm.org/D145766