[PATCH] D145766: [RISCV] Support Zfa fli instructions with vector splats.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/optional comment



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1544
+    // fli.h requires Zfh or Zvfh, but we might only have Zfhmin.
+    if (VT == MVT::f16 &&
+        (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh()) &&
----------------
Style: This really should be a switch on VT with a return in each block.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1550
+      return true;
+    if (VT == MVT::f64 && RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1)
+      return true;
----------------
Hm, shouldn't this depend on having the D extension?  (follow on)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145766/new/

https://reviews.llvm.org/D145766