[PATCH] D142998: [SVE][codegen] Add few more tests for MUL followed by ADD/SUB (NFC)

[Sushant Gokhale via Phabricator via llvm-commits]

sushgokh added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:10
+
+define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLA_ZPmZZ_B {{.*}}
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sushgokh wrote:
> paulwalker-arm wrote:
> > paulwalker-arm wrote:
> > > Please include equivalent tests for the other supports element types (i.e. i16, i32 and i64).
> > I forgot to mention. Please also add equivalent tests that are expected to result in FMAD/FMSB being emitted once the follow on patch lands.
> agreed. Thanks
Current tests in sve-generate-pseudo.ll are for MAD/MSB once the follow on patch lands.    i.e. currently, they are generating MLA/MLS but once the follow on patch lands, they will result in MAD/MSB being generated.

So, thanks. Will add assembly instructions as well in the check lines to indicate actual instruction generated


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142998/new/

https://reviews.llvm.org/D142998