[PATCH] D142998: [SVE][codegen] Add few more tests for MUL followed by ADD/SUB (NFC)

[Sushant Gokhale via Phabricator via llvm-commits]

sushgokh added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:4
+define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLS_ZPmZZ_B {{.*}}
+  %1 = mul <vscale x 16 x i8> %a, %b
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paulwalker-arm wrote:
> Please use `update_llc_test_checks.py` to autogenerate the `CHECK` lines.  Or perhaps why not just place all the tests within sve-int-arith.ll? given they're related.
I am not autogenerating because we just want to check the pseudo instruction thats generated. I suppose we arent interested in other instructions. Will add tests for other types.

I have not added them to sve-int-arith.ll for reason that:
1. Want to avoid auto-generation as said above
2. File name clearly states the purpose 


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Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:10
+
+define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLA_ZPmZZ_B {{.*}}
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paulwalker-arm wrote:
> paulwalker-arm wrote:
> > Please include equivalent tests for the other supports element types (i.e. i16, i32 and i64).
> I forgot to mention. Please also add equivalent tests that are expected to result in FMAD/FMSB being emitted once the follow on patch lands.
agreed. Thanks


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142998/new/

https://reviews.llvm.org/D142998