[PATCH] D142998: [SVE][codegen] Add few more tests for MUL followed by ADD/SUB (NFC)

Mon Mar 6 05:08:05 PST 2023

paulwalker-arm added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:4
+define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLS_ZPmZZ_B {{.*}}
+  %1 = mul <vscale x 16 x i8> %a, %b
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sushgokh wrote:
> paulwalker-arm wrote:
> > Please use `update_llc_test_checks.py` to autogenerate the `CHECK` lines.  Or perhaps why not just place all the tests within sve-int-arith.ll? given they're related.
> I am not autogenerating because we just want to check the pseudo instruction thats generated. I suppose we arent interested in other instructions. Will add tests for other types.
> 
> I have not added them to sve-int-arith.ll for reason that:
> 1. Want to avoid auto-generation as said above
> 2. File name clearly states the purpose 
The rational here does not make sense to me as the use of pseudo instructions it not revenant from a testing point of view. These tests are simply to show the expected output from a given blob of IR.

That said, after looking at `sve-int-arith.ll` I can see now that these are just clones of existing tests (mla_i8 and mls_i8) and so what I'm really asking for is this patch to extend those tests within `sve-int-arith.ll` to cover the other element types for all of mla, mad, mls, and msb.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142998/new/

https://reviews.llvm.org/D142998