[PATCH] D145002: [DAGCombiner] Make `(zext (sgt X, -1))` -> `(srl (not X), N-1)` work if typeof(zext)!=typeof(X)

[Noah Goldstein via Phabricator via llvm-commits]

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`(srl (not X), N-1)` is either 0/1, so any `zext` can be combined to
this.

To avoid the transformation when the result of the `setcc` is being
used directly, only allow mismatch if the `zext` type is larger than
`i8`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145002

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
  llvm/test/CodeGen/PowerPC/setcc-logic.ll
  llvm/test/CodeGen/PowerPC/signbit-shift.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
  llvm/test/CodeGen/X86/icmp-opt.ll
  llvm/test/CodeGen/X86/select-constant-xor.ll
  llvm/test/CodeGen/X86/select.ll

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