[PATCH] D145002: [DAGCombiner] Make `(zext (sgt X, -1))` -> `(srl (not X), N-1)` work if typeof(zext)!=typeof(X)

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12711
+      (VT == XVT ||
+       (VT.getSizeInBits() > 8 && N->getOpcode() == ISD::ZERO_EXTEND))) {
     // Invert and smear/shift the sign bit:
----------------
Should this be behind a new `TLI` flag? Particularly not sure if the `i8` case is generic or just `x86`.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145002/new/

https://reviews.llvm.org/D145002