[PATCH] D144229: [RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 17 10:35:41 PST 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:698
+ const unsigned Msb = MsbPlusOne - 1;
+ const unsigned Lsb = RightShAmt - LeftShAmt;
+
----------------
What if LeftShAmt > RightShAmt?
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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1008
+ // -> (<bfextract> x, msb, lsb)
+ const unsigned Msb = llvm::bit_width(C1) + C2 - 1;
+ const unsigned Lsb = C2;
----------------
This can overflow is C2 is larger than the number of leading zeros in C1. That's what the `if (C2 < Leading)` at line 1014 is protecting. I think you want to be below that and probably below the SRLIW check at line 1016.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144229/new/
https://reviews.llvm.org/D144229
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