[PATCH] D143754: [MachineInstr] Introduce generic predicated copy opcode

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

In D143754#4132515 <https://reviews.llvm.org/D143754#4132515>, @cdevadas wrote:

> The IsPredicable field will always be turned to 1 for Pred_Copy to indicate that it is the Predicated version of the copy.
>
> I actually wanted to have the Pred_Copy without these implicit operands. We should be able to model the dependency using an additional operand.
> But I don't know how to model this operand and hence decided to continue using the implicit operand itself.
>
> May be an immediate operand that takes const values (0, 1, 2, etc.)? 
> The immediate values can be mapped to enumerations defined via target files to represent these predicated dependencies.
> When there is no dependency, use the value 0. It means, there is no dependency and can change to the regular COPY.
> If required, the Pred_Copy with Imm_opnd value 0 can also be modeled for the "predicate is false" scenario.
>
> For example. the following can be defined for AMDGPU target in llvm/lib/Target/AMDGPU/SIDefines.h
>
> enum Copy_Predication {
>
>   None = 0,    // No dependency. It is for SGPR copies. At some point, convert the instruction into regular COPY.
>   Lane_Copy,  // copy only the active lanes of VGPRs.
>   Wave_Copy // copy all lanes of VGPRs
>
> }
>
> Any thoughts?

This would still be very target specific. And since all instructions with isPredicable=1 in my target takes 3 extra operands, then I assume other targets can have similar rules that should be fulfilled for such instructions. So if target generic opcodes starts to use isPredicable=1 it might end up a bit messy as such target sepcific expectations on TargetInstrInfo::isPredicable() isn't fulfilled.

I also agree with others that this feels quite target specific for AMDGPU (but that also makes me feel that maybe I've misunderstood why you want to make this generic).


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