[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:175
+static bool isEarlyClobberMI(MachineInstr &MI) {
+  return llvm::any_of(MI.defs(), [&](const MachineOperand &DefMO) {
+    return DefMO.isReg() && DefMO.isEarlyClobber();
----------------
Do we need `[&]` here or would `[]` work?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735