[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension

[Manolis Tsamis via Phabricator via llvm-commits]

mtsamis marked 2 inline comments as done.
mtsamis added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9744
+  MachineMemOperand *NewMMO = MF.getMachineMemOperand(
+      MMO, MMO->getPointerInfo(), MemVT == MVT::i32 ? 8 : 16);
+
----------------
craig.topper wrote:
> mtsamis wrote:
> > craig.topper wrote:
> > > Since the offset allows for a gap in the memory locations the size isn't 8/16. It needs to be UnknownSize or large enough to cover the gap.
> > The offset does not allow for a gap, all loads stores are from adjacent memory locations.
> > The offset only affects the base pointer from which the load/store happens.
> > 
> > E.g. per the specification:
> >   addr := rs1 + (zero_extend(imm2) << 4)
> >   tmp1 := mem[addr+7:addr]
> >   tmp2 := mem[addr+15:addr+8]
> > 
> > Would that make the 8/16 correct then?
> Yes. You're right. Sorry about that.
No problem, marking as done then


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https://reviews.llvm.org/D144002