[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9744
+  MachineMemOperand *NewMMO = MF.getMachineMemOperand(
+      MMO, MMO->getPointerInfo(), MemVT == MVT::i32 ? 8 : 16);
+
----------------
mtsamis wrote:
> craig.topper wrote:
> > Since the offset allows for a gap in the memory locations the size isn't 8/16. It needs to be UnknownSize or large enough to cover the gap.
> The offset does not allow for a gap, all loads stores are from adjacent memory locations.
> The offset only affects the base pointer from which the load/store happens.
> 
> E.g. per the specification:
>   addr := rs1 + (zero_extend(imm2) << 4)
>   tmp1 := mem[addr+7:addr]
>   tmp2 := mem[addr+15:addr+8]
> 
> Would that make the 8/16 correct then?
Yes. You're right. Sorry about that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144002/new/

https://reviews.llvm.org/D144002