[PATCH] D144092: [RISCV] Lower interleave and deinterleave intrinsics

[Luke Lau via Phabricator via llvm-commits]

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Lower the two intrinsics introduced in D141924 <https://reviews.llvm.org/D141924>.
Unfortunately there are no native interleave + deinterleave instructions
on RISC-V, so we need to use quite a lot of vrgathers here.

For deinterleaving, we can construct two indices of even and odd indices
and then gather the original vectors out of the larger, concatenated
vector.
For interleaving it's a bit trickier. We need to first create two
vector masks of alternating bits (... 0 1 0 1 for the even elements and
... 1 0 1 0) for the odd elements).
Then we "decompress" the source vector with a mask so that we place the
source vector elements in the right lanes.

Although the code generated for these intrinsics is not ideal, these
intrinsics can be combined with loads and stores into the much more
efficient segmented load and store instructions in a following patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144092

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

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