[PATCH] D143838: [X86] Improve (select carry C1+1 C1)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:50119
+  // equivalent to a SUB/ADD, respectively.
+  if (N0.getOpcode() == ISD::ZERO_EXTEND &&
+      N0.getOperand(0).getOpcode() == X86ISD::SETCC && N0.hasOneUse()) {
----------------
goldstein.w.n wrote:
> Do you need to check that `N0` is getting zero-extended to the same `VT` as `N1`?
> 
> Also can you do sign-extend as well and swap `sbb/adc`?
As long as N0 and N1 both are operands of the XOR/OR they should always have the same type. We don't allow mixed types on XOR/OR.

sign-extend wouldn't work because the X86ISD::SETCC node returns an i8 where bits 7:1 are 0. It corresponds to the SETcc instruction. So sign-extend would be sign extending bit 7 which isn't useful. It should have already been turned into zero-extend.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143838/new/

https://reviews.llvm.org/D143838