[PATCH] D143838: [X86] Improve (select carry C1+1 C1)

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:50119
+  // equivalent to a SUB/ADD, respectively.
+  if (N0.getOpcode() == ISD::ZERO_EXTEND &&
+      N0.getOperand(0).getOpcode() == X86ISD::SETCC && N0.hasOneUse()) {
----------------
Do you need to check that `N0` is getting zero-extended to the same `VT` as `N1`?

Also can you do sign-extend as well and swap `sbb/adc`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143838/new/

https://reviews.llvm.org/D143838