[PATCH] D144018: [AArch64] More consistently use buildvector for zero and all-ones constants

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, john.brawn, jaykang10, david-arm, bipmis.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

The AArch64 backend will use BUILDVECTORs for zero vectors or all-ones vectors, so during selection tablegen patterns get rely on immAllZerosV and immAllOnesV pattern frags in patters like `vnot`. It was not always consistent though, which this patch attempt to fix by recognizing where constant splat + insert vector element is used. The main outcome of this will be that full vector `movi v0.2d, #0000000000000000` will be used as opposed to `movi d0, #0`, as per https://reviews.llvm.org/D53579. This helps simplify what tablegen will see, to make pattern matching simpler.


https://reviews.llvm.org/D144018

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/build-one-lane.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
  llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D144018.497326.patch
Type: text/x-patch
Size: 11693 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230214/db1e55b7/attachment.bin>