[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:149
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+  MachineRegisterInfo *MRI = &(MBB.getParent()->getRegInfo());
+  MachineInstr &MI = *MBBI;
----------------
craig.topper wrote:
> I kind of think we should keep these instructions all the way to `RISCVAsmPrinter::emitInstruction`. Setting the operands to "undef" says it is ok to change the operands after this pass runs, but its not.  RISCVExpandPseudo runs late enough there is probably no pass that will change them. Keeping the pseudo all the way to `RISCVAsmPrinter::emitInstruction` removes any possibility.
Skip `PseudoRVVInitUndefM1|2|4|8` in `RISCVAsmPrinter::emitInstruction` and remove undef-init relate function in `RISCVExpandPseudo`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735