[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg marked 8 inline comments as done.
BeMg added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:151
+    bool TiedToDef = false;
+    for (MachineOperand &UseMO : UserMI->operands()) {
+      if (!UseMO.isReg())
----------------
craig.topper wrote:
> Do we need to scan all operands? Can we check if MO is a tied use and find the operand it is tied to check the early clobber?
```
0B      bb.0.entry:
16B       LIFETIME_START %stack.0.dst
32B       %1:vr = IMPLICIT_DEF
48B       early-clobber %0:vr = PseudoVRGATHER_VI_M1 killed %1:vr, 0, 0, 5
64B       %2:gpr = ADDI %stack.0.dst, 0
80B       PseudoVSE32_V_M1 killed %0:vr, killed %2:gpr, 0, 5
96B       LIFETIME_END %stack.0.dst
112B      %3:gpr = COPY $x0
128B      $x10 = COPY %3:gpr
144B      PseudoRET implicit $x10
```

Here we maybe need scan both defs and uses operand, because the early-clobber operand not always exist tied-to operand.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735