[PATCH] D143847: [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension

[Philipp Tomsich via Phabricator via llvm-commits]

philipp.tomsich updated this revision to Diff 497268.
philipp.tomsich added a comment.

- introduce sexti16 as a complex pattern (matches values that are sign-extended to an i16 and returns the underlying node --- i.e, what is being fed into the sign-extension)
- refactors sexti32 to share implementation with sexti16 (similarily to what is implemented for zexti32)
- simplifies XTHeadMac implementation by matching sexti16 instead of having multiple cases spelled out for shl+sra and sext_inreg


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143847/new/

https://reviews.llvm.org/D143847

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/xtheadmac.ll
  llvm/test/MC/RISCV/rv32xtheadmac-invalid.s
  llvm/test/MC/RISCV/rv32xtheadmac-valid.s
  llvm/test/MC/RISCV/rv64xtheadmac-valid.s
  llvm/test/MC/RISCV/xtheadmac-invalid.s

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