[PATCH] D142594: [AArch64] Eliminating the use of integer unit in moving from a Neon scalar result of a uaddlv to a Neon vector
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 13 01:59:11 PST 2023
dmgreen added a comment.
Thanks - this looks like it should be pretty generic.
================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:548-552
+ if (!MI.isRegTiedToDefOperand(1))
+ return false;
+
+ if (!MI.getOperand(2).isImm())
+ return false;
----------------
Will these ever not be true?
================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:564
+
+ if(!SrcMI->getOperand(1).getReg().isVirtual()) {
+ return false;
----------------
Please clang-format. You can also drop the brackets from single-statement if's.
Is it worth checking that the subreg indices are as-expected? I'm not sure they can actually be incorrect.
================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:582
+ .add(MI.getOperand(2))
+ .addUse(SrcReg, RegState::Kill)
+ .addImm(0);
----------------
It may not be Killed if it has other uses.
================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:587
+ LLVM_DEBUG(dbgs() << "Removed: " << ReplaceMI << "\n");
+ ReplaceMI->eraseFromParent();
+ }
----------------
If this is removing instructions, does it need to check that the COPYs have 1 use?
Could it just remove MI and let the others be removed naturally if they are no longer used?
================
Comment at: llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll:3376
; CHECK: // %bb.0:
-; CHECK-NEXT: mov d16, v0.d[1]
-; CHECK-NEXT: mov w8, #127
-; CHECK-NEXT: fcvtzs w11, d0
-; CHECK-NEXT: mov w9, #-128
-; CHECK-NEXT: fcvtzs w13, d1
-; CHECK-NEXT: mov d0, v2.d[1]
-; CHECK-NEXT: fcvtzs w14, d2
-; CHECK-NEXT: fcvtzs w10, d16
-; CHECK-NEXT: mov d16, v1.d[1]
-; CHECK-NEXT: mov d1, v3.d[1]
-; CHECK-NEXT: fcvtzs w15, d0
-; CHECK-NEXT: cmp w10, #127
-; CHECK-NEXT: csel w10, w10, w8, lt
-; CHECK-NEXT: fcvtzs w12, d16
-; CHECK-NEXT: cmn w10, #128
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: cmp w11, #127
-; CHECK-NEXT: csel w11, w11, w8, lt
-; CHECK-NEXT: cmn w11, #128
-; CHECK-NEXT: csel w11, w11, w9, gt
-; CHECK-NEXT: cmp w12, #127
-; CHECK-NEXT: csel w12, w12, w8, lt
-; CHECK-NEXT: cmn w12, #128
-; CHECK-NEXT: csel w12, w12, w9, gt
-; CHECK-NEXT: cmp w13, #127
-; CHECK-NEXT: csel w13, w13, w8, lt
-; CHECK-NEXT: fmov s0, w11
-; CHECK-NEXT: cmn w13, #128
-; CHECK-NEXT: csel w11, w13, w9, gt
-; CHECK-NEXT: cmp w15, #127
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: csel w10, w15, w8, lt
-; CHECK-NEXT: cmn w10, #128
-; CHECK-NEXT: fcvtzs w13, d3
-; CHECK-NEXT: fmov s2, w11
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: cmp w14, #127
-; CHECK-NEXT: fcvtzs w11, d1
-; CHECK-NEXT: mov w15, v0.s[1]
-; CHECK-NEXT: csel w14, w14, w8, lt
-; CHECK-NEXT: mov v2.s[1], w12
-; CHECK-NEXT: cmn w14, #128
-; CHECK-NEXT: csel w12, w14, w9, gt
-; CHECK-NEXT: cmp w11, #127
-; CHECK-NEXT: csel w11, w11, w8, lt
-; CHECK-NEXT: mov d1, v4.d[1]
-; CHECK-NEXT: mov v0.b[1], w15
-; CHECK-NEXT: cmn w11, #128
-; CHECK-NEXT: fmov w14, s2
-; CHECK-NEXT: csel w11, w11, w9, gt
-; CHECK-NEXT: fmov s3, w12
-; CHECK-NEXT: cmp w13, #127
-; CHECK-NEXT: mov w12, v2.s[1]
-; CHECK-NEXT: csel w13, w13, w8, lt
-; CHECK-NEXT: mov v0.b[2], w14
-; CHECK-NEXT: cmn w13, #128
-; CHECK-NEXT: mov v3.s[1], w10
-; CHECK-NEXT: csel w13, w13, w9, gt
-; CHECK-NEXT: fcvtzs w15, d1
-; CHECK-NEXT: fcvtzs w14, d4
-; CHECK-NEXT: mov d1, v5.d[1]
-; CHECK-NEXT: mov v0.b[3], w12
-; CHECK-NEXT: fmov s4, w13
-; CHECK-NEXT: cmp w15, #127
-; CHECK-NEXT: fmov w13, s3
-; CHECK-NEXT: csel w10, w15, w8, lt
-; CHECK-NEXT: mov w12, v3.s[1]
-; CHECK-NEXT: cmn w10, #128
-; CHECK-NEXT: fcvtzs w15, d1
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: cmp w14, #127
-; CHECK-NEXT: mov v0.b[4], w13
-; CHECK-NEXT: csel w14, w14, w8, lt
-; CHECK-NEXT: mov v4.s[1], w11
-; CHECK-NEXT: cmn w14, #128
-; CHECK-NEXT: csel w14, w14, w9, gt
-; CHECK-NEXT: fcvtzs w13, d5
-; CHECK-NEXT: cmp w15, #127
-; CHECK-NEXT: mov d2, v6.d[1]
-; CHECK-NEXT: mov v0.b[5], w12
-; CHECK-NEXT: csel w11, w15, w8, lt
-; CHECK-NEXT: fmov w12, s4
-; CHECK-NEXT: cmn w11, #128
-; CHECK-NEXT: fmov s1, w14
-; CHECK-NEXT: csel w11, w11, w9, gt
-; CHECK-NEXT: cmp w13, #127
-; CHECK-NEXT: mov w14, v4.s[1]
-; CHECK-NEXT: mov v0.b[6], w12
-; CHECK-NEXT: csel w13, w13, w8, lt
-; CHECK-NEXT: mov v1.s[1], w10
-; CHECK-NEXT: cmn w13, #128
-; CHECK-NEXT: fcvtzs w15, d2
-; CHECK-NEXT: csel w13, w13, w9, gt
-; CHECK-NEXT: fcvtzs w10, d6
-; CHECK-NEXT: mov v0.b[7], w14
-; CHECK-NEXT: cmp w15, #127
-; CHECK-NEXT: fmov w14, s1
-; CHECK-NEXT: csel w12, w15, w8, lt
-; CHECK-NEXT: fmov s2, w13
-; CHECK-NEXT: mov w13, v1.s[1]
-; CHECK-NEXT: mov d1, v7.d[1]
-; CHECK-NEXT: cmn w12, #128
-; CHECK-NEXT: fcvtzs w15, d7
-; CHECK-NEXT: csel w12, w12, w9, gt
-; CHECK-NEXT: cmp w10, #127
-; CHECK-NEXT: mov v0.b[8], w14
-; CHECK-NEXT: csel w10, w10, w8, lt
-; CHECK-NEXT: mov v2.s[1], w11
-; CHECK-NEXT: cmn w10, #128
-; CHECK-NEXT: fcvtzs w11, d1
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: mov v0.b[9], w13
-; CHECK-NEXT: fmov w14, s2
-; CHECK-NEXT: cmp w11, #127
-; CHECK-NEXT: fmov s1, w10
-; CHECK-NEXT: csel w10, w11, w8, lt
-; CHECK-NEXT: cmn w10, #128
-; CHECK-NEXT: mov w13, v2.s[1]
-; CHECK-NEXT: mov v0.b[10], w14
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: cmp w15, #127
-; CHECK-NEXT: mov v1.s[1], w12
-; CHECK-NEXT: csel w8, w15, w8, lt
-; CHECK-NEXT: cmn w8, #128
-; CHECK-NEXT: csel w8, w8, w9, gt
-; CHECK-NEXT: mov v0.b[11], w13
-; CHECK-NEXT: fmov w9, s1
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w8, v1.s[1]
-; CHECK-NEXT: mov v0.b[12], w9
-; CHECK-NEXT: mov v2.s[1], w10
-; CHECK-NEXT: mov v0.b[13], w8
-; CHECK-NEXT: fmov w8, s2
-; CHECK-NEXT: mov w9, v2.s[1]
-; CHECK-NEXT: mov v0.b[14], w8
-; CHECK-NEXT: mov v0.b[15], w9
-; CHECK-NEXT: ret
+; CHECK-NEXT: mov d16, v0.d[1]
+; CHECK-NEXT: mov w8, #127
----------------
Are you using llvm/utils/update_llc_test_checks.py on the file? I'm not sure the indenting should change.
================
Comment at: llvm/test/CodeGen/AArch64/peephole-insvigpr.mir:112
+ - { reg: '$x0', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
----------------
Some of this can often be removed to make the tests a little simple.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142594/new/
https://reviews.llvm.org/D142594
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