[PATCH] D143394: [RISCV] Add performMULcombine to perform strength-reduction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8579
+  SDValue N1 = N->getOperand(1);
+  ConstantSDNode *ConstOpOrElement = isConstOrConstSplat(N1);
+
----------------
Why allowing for vector?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8617
+
+    auto isDivisbleByShiftedAddConst = [&](APInt C, APInt &N, APInt &Quotient) {
+      unsigned BitWidth = C.getBitWidth();
----------------
Divisible*


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8645
+                 ? Value
+                 : DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Value);
+    };
----------------
It's harmless to create a nop ANY_EXTEND. getNode detects it.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8650
+                 ? Value
+                 : DAG.getNode(ISD::TRUNCATE, DL, VT, Value);
+    };
----------------
It's harmless to create a nop TRUNCATE.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8692
+    // C has 2 bits set: synthesize using 2 shifts and 1 add (which may
+    // see one of the shifts merged into a shift-and-add, if feasiblexs)
+    if (C.countPopulation() == 2) {
----------------
feasible*


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143394/new/

https://reviews.llvm.org/D143394