[llvm] 65ece07 - [RISCV] Replace condition that should alwasy be true with an assert. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-04T16:26:18-08:00
New Revision: 65ece07e0222b090c35686a91af5b161acc0f8e3

URL: https://github.com/llvm/llvm-project/commit/65ece07e0222b090c35686a91af5b161acc0f8e3
DIFF: https://github.com/llvm/llvm-project/commit/65ece07e0222b090c35686a91af5b161acc0f8e3.diff

LOG: [RISCV] Replace condition that should alwasy be true with an assert. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 2f7133b2ab75..636925b61e3d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -688,10 +688,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
 
   switch (Opcode) {
   case ISD::Constant: {
+    assert(VT == Subtarget->getXLenVT() && "Unexpected VT");
     auto *ConstNode = cast<ConstantSDNode>(Node);
-    if (VT == XLenVT && ConstNode->isZero()) {
+    if (ConstNode->isZero()) {
       SDValue New =
-          CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, XLenVT);
+          CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, VT);
       ReplaceNode(Node, New.getNode());
       return;
     }