[PATCH] D142281: [AVR] Optimize 16-bit comparison with a constant

[Ben Shi via Phabricator via llvm-commits]

benshi001 created this revision.
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Fixes https://github.com/llvm/llvm-project/issues/30923


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142281

Files:
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/test/CodeGen/AVR/cmp.ll


Index: llvm/test/CodeGen/AVR/cmp.ll
===================================================================
--- llvm/test/CodeGen/AVR/cmp.ll
+++ llvm/test/CodeGen/AVR/cmp.ll
@@ -202,3 +202,40 @@
 if.end:
   ret void
 }
+
+define i16 @cmp_i16_gt_0(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_0:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi r18, 1
+; CHECK-NEXT:    cp  r1, r24
+; CHECK-NEXT:    cpc r1, r25
+; CHECK-NEXT:    brlt
+  %2 = icmp sgt i16 %0, 0
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}
+
+define i16 @cmp_i16_gt_126(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_126:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi  r18, 1
+; CHECK-NEXT:    cpi  r24, 127
+; CHECK-NEXT:    cpc  r25, r1
+; CHECK-NEXT:    brge
+  %2 = icmp sgt i16 %0, 126
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}
+
+define i16 @cmp_i16_gt_1023(i16 %0) {
+; CHECK-LABEL: cmp_i16_gt_1023:
+; CHECK:       %bb.0:
+; CHECK-NEXT:    ldi  r19, 4
+; CHECK-NEXT:    ldi  r18, 1
+; CHECK-NEXT:    cp   r24, r1
+; CHECK-NEXT:    cpc  r25, r19
+; CHECK-NEXT:    brge
+  %2 = icmp sgt i16 %0, 1023
+  %3 = zext i1 %2 to i16
+  ret i16 %3
+}
Index: llvm/lib/Target/AVR/AVRISelLowering.cpp
===================================================================
--- llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -634,11 +634,32 @@
   SDValue Cmp;
 
   if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
+    uint64_t Imm = cast<ConstantSDNode>(RHS)->getZExtValue();
     // Generate a CPI/CPC pair if RHS is a 16-bit constant.
     SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                                 DAG.getIntPtrConstant(0, DL));
     SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
                                 DAG.getIntPtrConstant(1, DL));
+    SDValue RHSlo, RHShi;
+    if ((Imm & 0xff) != 0)
+      RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+                          DAG.getIntPtrConstant(0, DL));
+    else // Use the zero register instead of a zero immediate.
+      RHSlo = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    if ((Imm & 0xff00) != 0)
+      RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+                          DAG.getIntPtrConstant(1, DL));
+    else // Use the zero register instead of a zero immediate.
+      RHShi = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
+    Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
+  } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(LHS)) {
+    uint64_t Imm = cast<ConstantSDNode>(RHS)->getZExtValue();
+    if (Imm != 0)
+      llvm_unreachable("unexpected i16 comparison node");
+    // Generate a CPI/CPC pair.
+    SDValue LHSlo = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
+    SDValue LHShi = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
     SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
                                 DAG.getIntPtrConstant(0, DL));
     SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,


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