[PATCH] D141653: [X86] Improve instruction ordering of constant `srl/shl` with `and` to get better and-masks

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 490567.
goldstein.w.n marked an inline comment as done.
goldstein.w.n added a comment.

Fix nits + improve comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141653/new/

https://reviews.llvm.org/D141653

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/avx512-calling-conv.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/bmi-x86_64.ll
  llvm/test/CodeGen/X86/bmi.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/combine-rotates.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/fold-and-shift.ll
  llvm/test/CodeGen/X86/limited-prec.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/pr15267.ll
  llvm/test/CodeGen/X86/pr45995.ll
  llvm/test/CodeGen/X86/pull-binop-through-shift.ll
  llvm/test/CodeGen/X86/rev16.ll
  llvm/test/CodeGen/X86/rotate-extract.ll
  llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
  llvm/test/CodeGen/X86/setcc.ll
  llvm/test/CodeGen/X86/shift-amount-mod.ll
  llvm/test/CodeGen/X86/shift-mask.ll
  llvm/test/CodeGen/X86/sttni.ll
  llvm/test/CodeGen/X86/tbm_patterns.ll
  llvm/test/CodeGen/X86/udiv_fix.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D141653.490567.patch
Type: text/x-patch
Size: 130244 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230119/75e75662/attachment.bin>