[PATCH] D142025: [AArch64][SME2] Add multi-vector FP convert from Float to interleave Half/BFloat intrinsic

Thu Jan 19 01:34:30 PST 2023

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM!

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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2,+bf16 -verify-machineinstrs < %s | FileCheck %s
+
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nit: Perhaps you can remove the '+sve' flag before merging, since I don't think it's needed.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142025/new/

https://reviews.llvm.org/D142025