[PATCH] D141601: [AArch64][SME2] MOVA tile-to-vector and vector-to-tile should not accept VG suffix

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 18 06:24:11 PST 2023


sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3243
 
 class sme2_mova_tile_to_vec_vg2_multi_base<bits<2> sz, bit v, bits<3> op,
                                            RegisterOperand vector_ty,
----------------
MattDevereau wrote:
> Given that `vgx2` has been removed from this class is it not misleading to still have `vg2` in the class and multiclass name? Same goes for the `vgx4` variants.
That's probably best done in a separate NFC patch, because it makes this change quite big. It would also mean changing the naming scheme for lots of other instructions (e.g. `defm ZIP_VG2_2ZZZ : sme2_zip_vector_vg2<"zip", 0b0>;`) which also uses `vg2` to mean "two vectors".


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141601/new/

https://reviews.llvm.org/D141601



More information about the llvm-commits mailing list