[PATCH] D141258: [AArch64] Fix crash for expandMOVImm

[Allen zhong via Phabricator via llvm-commits]

Allen updated this revision to Diff 489998.
Allen added a comment.

Stick the bitsize check in the caller according comment, AArch64TargetLowering::isMulAddWithConstProfitable


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141258/new/

https://reviews.llvm.org/D141258

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/const-isel.ll


Index: llvm/test/CodeGen/AArch64/const-isel.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/const-isel.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=FISEL
+
+define i53 @PR59892 () {
+; FISEL-LABEL: PR59892:
+; FISEL:       // %bb.0:
+; FISEL-NEXT:    mov x8, #47668
+; FISEL-NEXT:    movk x8, #4645, lsl #16
+; FISEL-NEXT:    movk x8, #58741, lsl #32
+; FISEL-NEXT:    movk x8, #1, lsl #48
+; FISEL-NEXT:    orr x9, x8, #0x2
+; FISEL-NEXT:    mul x0, x9, x8
+; FISEL-NEXT:    ret
+  %a = mul nsw i53 533765955107380, 533765955107382
+  ret i53 %a
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9797,8 +9797,7 @@
     // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
     // movw+movk is fused). So we limit up to 2 instrdduction at most.
     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
-    AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(),
-			      Insn);
+    AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);
     unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 5 : 2));
     IsLegal = Insn.size() <= Limit;
   }
@@ -14812,7 +14811,9 @@
   if (!isLegalAddImmediate(C1) || isLegalAddImmediate(C1C2.getSExtValue()))
     return true;
   SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
-  AArch64_IMM::expandMOVImm(C1C2.getZExtValue(), VT.getSizeInBits(), Insn);
+  // Adapt to the width of a register.
+  unsigned BitSize = VT.getSizeInBits() <= 32 ? 32 : 64;
+  AArch64_IMM::expandMOVImm(C1C2.getZExtValue(), BitSize, Insn);
   if (Insn.size() > 1)
     return false;
 


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