[PATCH] D141061: [RISCV][InsertVSETVLI] Using rigth instruction during mutate AVL of vsetvli

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1319
             MI.getOperand(1).ChangeToRegister(NextMI->getOperand(1).getReg(), false);
+          if (MI.getOpcode() != NextMI->getOpcode())
+            MI.setDesc(TII->get(NextMI->getOpcode()));
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I think you can drop this `if`. `setDesc` is cheap.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1320
+          if (MI.getOpcode() != NextMI->getOpcode())
+            MI.setDesc(TII->get(NextMI->getOpcode()));
         }
----------------
`MI.setDesc(NextMI->getDesc())`?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141061/new/

https://reviews.llvm.org/D141061