[PATCH] D141060: [opt] Infer DataLayout from triple if not specified

[Alexander Richardson via Phabricator via llvm-commits]

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Haven't updated all tests this affects yet, wanted to check if this is an acceptable change before spending more time on it.


There are many tests that specify a target triple/CPU flags but no
DataLayout which can lead to IR being generated that has unusual
behaviour. This commit attempts to use the default DataLayout based
on the relevant flags if there is no explicit override on the command
line or in the IR file.

One thing that is not currently possible to differentiate from a missing
datalayout `target datalayout = ""` in the IR file since the current
APIs don't allow detecting this case. If it is considered useful to
support this case (instead of just using something basic like "e"),
I can change IR parsers to track whether they have seen such a
directive and change the callback type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141060

Files:
  llvm/test/Analysis/BasicAA/libfuncs.ll
  llvm/test/Analysis/CostModel/AMDGPU/cast.ll
  llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
  llvm/test/Analysis/CostModel/X86/trunc-codesize.ll
  llvm/test/Analysis/CostModel/X86/trunc-latency.ll
  llvm/test/Analysis/CostModel/X86/trunc-sizelatency.ll
  llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
  llvm/test/CodeGen/X86/expand-large-div-rem-sdiv129.ll
  llvm/test/CodeGen/X86/expand-large-div-rem-srem129.ll
  llvm/test/CodeGen/X86/expand-large-div-rem-udiv129.ll
  llvm/test/CodeGen/X86/expand-large-div-rem-urem129.ll
  llvm/test/Transforms/InstCombine/ffs-i16.ll
  llvm/test/Transforms/InstCombine/fls-i16.ll
  llvm/test/Transforms/InstCombine/isascii-i16.ll
  llvm/test/Transforms/InstCombine/isdigit-i16.ll
  llvm/test/Transforms/InstCombine/printf-i16.ll
  llvm/test/Transforms/InstCombine/puts-i16.ll
  llvm/test/Transforms/InstSimplify/ConstProp/calls-math-finite.ll
  llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
  llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
  llvm/test/Transforms/MergeICmps/X86/addressspaces.ll
  llvm/tools/opt/opt.cpp

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