[PATCH] D141061: [RISCV][InsertVSETVLI] Using rigth instruction during mutate AVL of vsetvli

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 5 07:47:14 PST 2023

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reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM

Sorry for the breakage, and thanks for the fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141061/new/

https://reviews.llvm.org/D141061

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