[PATCH] D140569: [AVR] Custom lower 32-bit shift instructions

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:303
+        cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    if (ShiftAmount == 16) {
+      // Special case these two operations because they appear to be used by the
----------------
Is this necessary? Can it be covered by https://reviews.llvm.org/D140570 ? 

If you think it is better to handle `ShiftAmount == 16` at here, I suggest you add tests for that in current patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140569/new/

https://reviews.llvm.org/D140569