[PATCH] D140831: Fix a phase-ordering problem in SimplifyCFG.

[Owen Anderson via Phabricator via llvm-commits]

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Switch simplification could sometimes fail to notice when an
intermediate case removal caused the switch condition to become
constant. This would cause the switch to be simplified into a
conditional branch rather than a direct branch.

Most of the time this didn't matter, except that occasionally
downstream parts of SimplifyCFG expect tautological branches to
already have been eliminated. The missed handling in switch
simplification would cause an assertion failure in the downstream
code.

Triggering the assertion failure is fairly sensitive to the exact
order of various simplifications.

Fixes https://github.com/llvm/llvm-project/issues/59768


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140831

Files:
  llvm/lib/Transforms/Utils/Local.cpp
  llvm/test/Transforms/SimplifyCFG/switch-simplify-crash2.ll


Index: llvm/test/Transforms/SimplifyCFG/switch-simplify-crash2.ll
===================================================================
--- /dev/null
+++ llvm/test/Transforms/SimplifyCFG/switch-simplify-crash2.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -O2 < %s | FileCheck %s
+
+define i8 @f(i1 %0) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:    br label [[DOTPEEL_BEGIN:%.*]]
+; CHECK:       .loopexit:
+; CHECK-NEXT:    br label [[DOTLOOPEXIT:%.*]]
+; CHECK:       .peel.begin:
+; CHECK-NEXT:    br i1 [[TMP0:%.*]], label [[DOTLOOPEXIT]], label [[DOTPEEL_BEGIN]]
+;
+  br label %6
+
+2:                                                ; preds = %8, %3
+  br i1 %0, label %8, label %6
+
+3:                                                ; preds = %6, %3
+  %.0 = phi i8 [ %.4, %6 ], [ 0, %3 ]
+  switch i8 %.0, label %5 [
+  i8 0, label %2
+  i8 1, label %3
+  ]
+
+4:                                                ; preds = %8, %5
+  %.1 = phi i8 [ %.2, %5 ], [ 1, %8 ]
+  br label %8
+
+5:                                                ; preds = %8, %7, %3
+  %.2 = phi i8 [ 0, %3 ], [ %.7, %7 ], [ 0, %8 ]
+  br label %4
+
+6:                                                ; preds = %2, %1
+  %.4 = phi i8 [ 0, %1 ], [ 1, %2 ]
+  br label %3
+
+7:                                                ; preds = %8
+  br label %5
+
+8:                                                ; preds = %8, %4, %2
+  %.7 = phi i8 [ %.1, %4 ], [ 0, %8 ], [ 2, %2 ]
+  switch i8 %.7, label %7 [
+  i8 0, label %5
+  i8 1, label %4
+  i8 4, label %8
+  i8 3, label %2
+  ]
+}
Index: llvm/lib/Transforms/Utils/Local.cpp
===================================================================
--- llvm/lib/Transforms/Utils/Local.cpp
+++ llvm/lib/Transforms/Utils/Local.cpp
@@ -237,6 +237,8 @@
         DefaultDest->removePredecessor(ParentBB);
         i = SI->removeCase(i);
         e = SI->case_end();
+        // Removing this case may have made the condition constant.
+        CI = dyn_cast<ConstantInt>(SI->getCondition());
         Changed = true;
         continue;
       }


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