[PATCH] D140676: [AArch64] `LowerZERO_EXTEND_VECTOR_INREG()`: recursively apply `zip1` until done
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 30 10:29:48 PST 2022
fhahn added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/zext-to-tbl.ll:1025
+; CHECK-NEXT: zip1.16b v1, v1, v0
+; CHECK-NEXT: zip1.8h v1, v1, v0
; CHECK-NEXT: str q1, [x1], #64
----------------
I think that for this lowering is slightly worse in general for CPUs that have efficient implementations of `tbl`, as `tbl` results in shorter dependency chains than having 2 `zip1`, with one depending on the other. The `tbl` lowering is only used in loops, when the load from the constant pool is hoisted outside the loop.
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https://reviews.llvm.org/D140676/new/
https://reviews.llvm.org/D140676
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