[PATCH] D140676: [AArch64] `LowerZERO_EXTEND_VECTOR_INREG()`: recursively apply `zip1` until done

[Roman Lebedev via Phabricator via llvm-commits]

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While the one-step `zip1` lowering seemed obviously good,
here i feel like i should double-check: is 2 or more `zip1`
not worse than a `tbl`?
I'm guessing so, because it avoids constant pool load.

This comes up in a follow-up change to `combineShuffleToZeroExtendVectorInReg()`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140676

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/zext-to-tbl.ll

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