[PATCH] D140665: [SelectionDAG][RISCV][X86][AArch64][AMDGPU][PowerPC] Improve SimplifyDemandedBits for SHL with NUW/NSW flags.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D140665#4017096 <https://reviews.llvm.org/D140665#4017096>, @liaolucy wrote:

> In D140665#4017069 <https://reviews.llvm.org/D140665#4017069>, @lebedev.ri wrote:
>
>> I think it shouldn't demand them. The only reason it "needs" them,
>> is to satisfy it's poison-generating flags. I think it would be better
>> to keep not demanding them, and drop the poison-generating flags.
>> For example consider:
>>
>>   %y = and %x, 15
>>   %z = shl nuw %y, 4
>>    =>
>>   %z = shl %x, 4
>>
>> Now if you demand the high bits (and only because of `nuw`!),
>> you suddenly can't look past the `and`.
>
> You do have a point, in fact I just want to optimize RISCV.

Having re-read the whole thread here, it is not obvious to me what is the original problem that is trying to be solved here?

> I have a question now, I see InstCombineSimplifyDemanded.cpp <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L635> has similar support, can you help to explain why?

Optimizations in back-end, including this one, are mainly to deal with
optimization opportiunities that arise during instruction lowering/legalization,
and other sequences that are not well-exploitable in generic IR.
OTOH, the middle-end optimizations is where the optimizations should happen in general.
It's likely the InstCombineSimplifyDemanded code has the same bug.


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