[PATCH] D140665: [SelectionDAG][RISCV][X86][AArch64][AMDGPU][PowerPC] Improve SimplifyDemandedBits for SHL with NUW/NSW flags.

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added a comment.

In D140665#4017069 <https://reviews.llvm.org/D140665#4017069>, @lebedev.ri wrote:

> I think it shouldn't demand them. The only reason it "needs" them,
> is to satisfy it's poison-generating flags. I think it would be better
> to keep not demanding them, and drop the poison-generating flags.
> For example consider:
>
>   %y = and %x, 15
>   %z = shl nuw %y, 4
>    =>
>   %z = shl %x, 4
>
> Now if you demand the high bits (and only because of `nuw`!),
> you suddenly can't look past the `and`.

You do have a point, in fact I just want to optimize RISCV.  I have a question now, I see InstCombineSimplifyDemanded.cpp <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L635> has similar support, can you help to explain why?


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https://reviews.llvm.org/D140665