[llvm] 00c7840 - [InstCombine] replace undef in vector tests with poison; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 26 10:37:13 PST 2022
Author: Sanjay Patel
Date: 2022-12-26T13:16:03-05:00
New Revision: 00c7840115fb742cd7278a5b3f5337990429ca47
URL: https://github.com/llvm/llvm-project/commit/00c7840115fb742cd7278a5b3f5337990429ca47
DIFF: https://github.com/llvm/llvm-project/commit/00c7840115fb742cd7278a5b3f5337990429ca47.diff
LOG: [InstCombine] replace undef in vector tests with poison; NFC
I left a few of the existing undef tests in place for extra
coverage and because one of those was noted as a miscompile in
the post-commit feedback for d4493dd1ed58ac3f1eab0, but we are
transitioning to poison, so it is more valuable to test the
expected IR going forward.
Added:
Modified:
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
llvm/test/Transforms/InstCombine/shl-sub.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
index 152a52a540a51..75de1dc6d07a2 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
@@ -25,8 +25,8 @@ define i1 @p0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -45,8 +45,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> <i8 1, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <2 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 1, i8 1>, %y
call void @use2i8(<2 x i8> %t0)
@@ -56,15 +56,15 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
ret <2 x i1> %ret
}
-define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p2_vec_undef0(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[Y:%.*]]
+define <3 x i1> @p2_vec_poison0(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p2_vec_poison0(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %y
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
%t1 = add <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
%t2 = and <3 x i8> %t1, %x
@@ -72,33 +72,33 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
ret <3 x i1> %ret
}
-define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p3_vec_undef0(
+define <3 x i1> @p3_vec_poison0(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p3_vec_poison0(
; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 1, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 1, i8 1, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%t2 = and <3 x i8> %t1, %x
%ret = icmp eq <3 x i8> %t2, %x
ret <3 x i1> %ret
}
-define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p4_vec_undef2(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[Y:%.*]]
+define <3 x i1> @p4_vec_poiso2(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p4_vec_poiso2(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %y
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%t2 = and <3 x i8> %t1, %x
%ret = icmp eq <3 x i8> %t2, %x
ret <3 x i1> %ret
@@ -116,8 +116,8 @@ define i1 @c0(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -134,8 +134,8 @@ define i1 @c1(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -152,8 +152,8 @@ define i1 @c2(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -174,8 +174,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -193,8 +193,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -213,8 +213,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp uge i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
index f1d1a06a56030..a92f4a9d95431 100644
--- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
+++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
@@ -25,8 +25,8 @@ define i1 @p0(i8 %x, i8 %y) {
; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -45,8 +45,8 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> <i8 1, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <2 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <2 x i1> [[RET]]
;
%t0 = shl <2 x i8> <i8 1, i8 1>, %y
call void @use2i8(<2 x i8> %t0)
@@ -56,15 +56,15 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) {
ret <2 x i1> %ret
}
-define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p2_vec_undef0(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[Y:%.*]]
+define <3 x i1> @p2_vec_poison0(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p2_vec_poison0(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %y
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
%t1 = add <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
%t2 = and <3 x i8> %t1, %x
@@ -72,33 +72,33 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
ret <3 x i1> %ret
}
-define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p3_vec_undef0(
+define <3 x i1> @p3_vec_poison0(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p3_vec_poison0(
; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 1, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
%t0 = shl <3 x i8> <i8 1, i8 1, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%t2 = and <3 x i8> %t1, %x
%ret = icmp ne <3 x i8> %t2, %x
ret <3 x i1> %ret
}
-define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) {
-; CHECK-LABEL: @p4_vec_undef2(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[Y:%.*]]
+define <3 x i1> @p4_vec_poison2(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @p4_vec_poison2(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[Y:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
-; CHECK-NEXT: ret <3 x i1> [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[RET]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %y
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %y
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%t2 = and <3 x i8> %t1, %x
%ret = icmp ne <3 x i8> %t2, %x
ret <3 x i1> %ret
@@ -116,8 +116,8 @@ define i1 @c0(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -134,8 +134,8 @@ define i1 @c1(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -152,8 +152,8 @@ define i1 @c2(i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[X:%.*]] = call i8 @gen8()
; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]]
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
@@ -174,8 +174,8 @@ define i1 @oneuse0(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T0]])
; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1
; CHECK-NEXT: call void @use8(i8 [[T1]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X:%.*]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -193,8 +193,8 @@ define i1 @oneuse1(i8 %x, i8 %y) {
; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0) ; needed anyway
@@ -213,8 +213,8 @@ define i1 @oneuse2(i8 %x, i8 %y) {
; CHECK-NEXT: call void @use8(i8 [[T1]])
; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use8(i8 [[T2]])
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[T1]], [[X]]
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[RET:%.*]] = icmp ult i8 [[T1]], [[X]]
+; CHECK-NEXT: ret i1 [[RET]]
;
%t0 = shl i8 1, %y
call void @use8(i8 %t0)
diff --git a/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
index b694ac0374c7a..2426d8cfb4d9b 100644
--- a/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
@@ -67,8 +67,23 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) {
ret <3 x i1> %r
}
-define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
-; CHECK-LABEL: @p2_vec_undef1(
+define <3 x i1> @p2_vec_poison0(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison0(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[BITS:%.*]]
+; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
+; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
+; CHECK-NEXT: [[R:%.*]] = icmp eq <3 x i8> [[VAL_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[R]]
+;
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %bits
+ call void @use3i8(<3 x i8> %t0)
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
+ %r = icmp uge <3 x i8> %t1, %val
+ ret <3 x i1> %r
+}
+
+define <3 x i1> @p2_vec_poison1(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison1(
; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 1, i8 1>, [[BITS:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
@@ -77,22 +92,22 @@ define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
;
%t0 = shl <3 x i8> <i8 1, i8 1, i8 1>, %bits
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%r = icmp uge <3 x i8> %t1, %val
ret <3 x i1> %r
}
-define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) {
-; CHECK-LABEL: @p2_vec_undef2(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[BITS:%.*]]
+define <3 x i1> @p2_vec_poison2(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison2(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[BITS:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
; CHECK-NEXT: [[R:%.*]] = icmp eq <3 x i8> [[VAL_HIGHBITS]], zeroinitializer
; CHECK-NEXT: ret <3 x i1> [[R]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %bits
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %bits
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%r = icmp uge <3 x i8> %t1, %val
ret <3 x i1> %r
}
diff --git a/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
index f9a4c9d2afeb5..bcfc898a0c249 100644
--- a/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
@@ -67,8 +67,23 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) {
ret <3 x i1> %r
}
-define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
-; CHECK-LABEL: @p2_vec_undef1(
+define <3 x i1> @p2_vec_poison0(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison0(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[BITS:%.*]]
+; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
+; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
+; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i8> [[VAL_HIGHBITS]], zeroinitializer
+; CHECK-NEXT: ret <3 x i1> [[R]]
+;
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %bits
+ call void @use3i8(<3 x i8> %t0)
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
+ %r = icmp ult <3 x i8> %t1, %val
+ ret <3 x i1> %r
+}
+
+define <3 x i1> @p2_vec_poison1(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison1(
; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 1, i8 1>, [[BITS:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
@@ -77,22 +92,22 @@ define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
;
%t0 = shl <3 x i8> <i8 1, i8 1, i8 1>, %bits
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%r = icmp ult <3 x i8> %t1, %val
ret <3 x i1> %r
}
-define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) {
-; CHECK-LABEL: @p2_vec_undef2(
-; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 undef, i8 1>, [[BITS:%.*]]
+define <3 x i1> @p2_vec_poison2(<3 x i8> %val, <3 x i8> %bits) {
+; CHECK-LABEL: @p2_vec_poison2(
+; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> <i8 1, i8 poison, i8 1>, [[BITS:%.*]]
; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]])
; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]]
; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i8> [[VAL_HIGHBITS]], zeroinitializer
; CHECK-NEXT: ret <3 x i1> [[R]]
;
- %t0 = shl <3 x i8> <i8 1, i8 undef, i8 1>, %bits
+ %t0 = shl <3 x i8> <i8 1, i8 poison, i8 1>, %bits
call void @use3i8(<3 x i8> %t0)
- %t1 = add <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
+ %t1 = add <3 x i8> %t0, <i8 -1, i8 poison, i8 -1>
%r = icmp ult <3 x i8> %t1, %val
ret <3 x i1> %r
}
diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
index 48b4680ddfc40..478e6bd5878d5 100644
--- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
+++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
@@ -89,13 +89,13 @@ define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
ret <8 x i32> %t7
}
-define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
-; CHECK-LABEL: @t2_vec_splat_undef(
-; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
+define <8 x i32> @t2_vec_splat_poison(<8 x i64> %x, <8 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec_splat_poison(
+; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64>
-; CHECK-NEXT: [[T2:%.*]] = shl nuw <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, [[T1]]
-; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
-; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = shl nuw <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 poison, i64 1>, [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 poison, i64 -1>
+; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
@@ -106,11 +106,11 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-NEXT: [[T7:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 poison, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T7]]
;
- %t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
+ %t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
%t1 = zext <8 x i32> %t0 to <8 x i64>
- %t2 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, %t1 ; shifting by nbits-1
- %t3 = add <8 x i64> %t2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
- %t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
+ %t2 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 poison, i64 1>, %t1 ; shifting by nbits-1
+ %t3 = add <8 x i64> %t2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 poison, i64 -1>
+ %t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, %nbits
call void @use8xi32(<8 x i32> %t0)
call void @use8xi64(<8 x i64> %t1)
diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
index c9872b2e20b3d..a9fafdbf7b8db 100644
--- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
+++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
@@ -71,12 +71,12 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) {
ret <8 x i32> %t5
}
-define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
-; CHECK-LABEL: @t1_vec_splat_undef(
-; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
-; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1>, [[T0]]
-; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
-; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
+define <8 x i32> @t1_vec_splat_poison(<8 x i32> %x, <8 x i32> %nbits) {
+; CHECK-LABEL: @t1_vec_splat_poison(
+; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
+; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 1>, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
+; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
@@ -85,11 +85,11 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) {
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 poison, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
- %t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
- %t1 = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1>, %t0
- %t2 = add <8 x i32> %t1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 undef, i32 -1>
+ %t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
+ %t1 = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 1>, %t0
+ %t2 = add <8 x i32> %t1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 poison, i32 -1>
%t3 = and <8 x i32> %t2, %x
- %t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
+ %t4 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, %nbits
call void @use8xi32(<8 x i32> %t0)
call void @use8xi32(<8 x i32> %t1)
call void @use8xi32(<8 x i32> %t2)
diff --git a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
index d177a2b13e443..e3bcfde4ad59c 100644
--- a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
+++ b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll
@@ -89,12 +89,12 @@ define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
ret <8 x i32> %t6
}
-define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
-; CHECK-LABEL: @t2_vec_splat_undef(
+define <8 x i32> @t2_vec_splat_poison(<8 x i64> %x, <8 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec_splat_poison(
; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
-; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, [[T0]]
-; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
-; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
+; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 poison, i64 1>, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 poison, i64 -1>
+; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, [[NBITS]]
; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
@@ -107,9 +107,9 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-NEXT: ret <8 x i32> [[T6]]
;
%t0 = zext <8 x i32> %nbits to <8 x i64>
- %t1 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, %t0
- %t2 = add <8 x i64> %t1, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
- %t3 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
+ %t1 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 poison, i64 1>, %t0
+ %t2 = add <8 x i64> %t1, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 poison, i64 -1>
+ %t3 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 poison, i32 32>, %nbits
%t4 = and <8 x i64> %t2, %x
call void @use8xi32(<8 x i32> %nbits)
diff --git a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
index d15e3a140775c..a7fd2717e7197 100644
--- a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
+++ b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
@@ -155,12 +155,12 @@ define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
ret <3 x i32> %t5
}
-define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
-; CHECK-LABEL: @t5_vec_undef(
-; CHECK-NEXT: [[T1:%.*]] = shl nuw <3 x i32> <i32 1, i32 undef, i32 1>, [[NBITS:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 undef, i32 -1>
+define <3 x i32> @t5_vec_poison(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t5_vec_poison(
+; CHECK-NEXT: [[T1:%.*]] = shl nuw <3 x i32> <i32 1, i32 poison, i32 1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 poison, i32 -1>
; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
-; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[NBITS]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 poison, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
@@ -169,11 +169,11 @@ define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[X]], [[T4]]
; CHECK-NEXT: ret <3 x i32> [[T5]]
;
- %t0 = add <3 x i32> %nbits, <i32 0, i32 undef, i32 0>
- %t1 = shl <3 x i32> <i32 1, i32 undef, i32 1>, %t0
- %t2 = add nsw <3 x i32> %t1, <i32 -1, i32 undef, i32 -1>
+ %t0 = add <3 x i32> %nbits, <i32 0, i32 poison, i32 0>
+ %t1 = shl <3 x i32> <i32 1, i32 poison, i32 1>, %t0
+ %t2 = add nsw <3 x i32> %t1, <i32 -1, i32 poison, i32 -1>
%t3 = and <3 x i32> %t2, %x
- %t4 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %nbits
+ %t4 = sub <3 x i32> <i32 32, i32 poison, i32 32>, %nbits
call void @use3xi32(<3 x i32> %t0)
call void @use3xi32(<3 x i32> %t1)
call void @use3xi32(<3 x i32> %t2)
diff --git a/llvm/test/Transforms/InstCombine/shl-sub.ll b/llvm/test/Transforms/InstCombine/shl-sub.ll
index 7cecd332a5bb8..332c748e775ed 100644
--- a/llvm/test/Transforms/InstCombine/shl-sub.ll
+++ b/llvm/test/Transforms/InstCombine/shl-sub.ll
@@ -56,13 +56,13 @@ define <2 x i64> @shl_sub_i64_vec(<2 x i64> %x) {
ret <2 x i64> %r
}
-define <3 x i64> @shl_sub_i64_vec_undef(<3 x i64> %x) {
-; CHECK-LABEL: @shl_sub_i64_vec_undef(
+define <3 x i64> @shl_sub_i64_vec_poison(<3 x i64> %x) {
+; CHECK-LABEL: @shl_sub_i64_vec_poison(
; CHECK-NEXT: [[R:%.*]] = lshr <3 x i64> <i64 -9223372036854775808, i64 -9223372036854775808, i64 -9223372036854775808>, [[X:%.*]]
; CHECK-NEXT: ret <3 x i64> [[R]]
;
%s = sub <3 x i64> <i64 63, i64 63, i64 63>, %x
- %r = shl <3 x i64> <i64 1, i64 undef, i64 1>, %s
+ %r = shl <3 x i64> <i64 1, i64 poison, i64 1>, %s
ret <3 x i64> %r
}
@@ -167,14 +167,14 @@ define <3 x i64> @shl_sub_i64_vec_undef_bad(<3 x i64> %x) {
ret <3 x i64> %r
}
-define <3 x i64> @shl_sub_i64_vec_undef_bad2(<3 x i64> %x) {
-; CHECK-LABEL: @shl_sub_i64_vec_undef_bad2(
-; CHECK-NEXT: [[S:%.*]] = sub <3 x i64> <i64 63, i64 undef, i64 63>, [[X:%.*]]
-; CHECK-NEXT: [[R:%.*]] = shl nuw <3 x i64> <i64 1, i64 undef, i64 1>, [[S]]
+define <3 x i64> @shl_sub_i64_vec_poison_bad2(<3 x i64> %x) {
+; CHECK-LABEL: @shl_sub_i64_vec_poison_bad2(
+; CHECK-NEXT: [[S:%.*]] = sub <3 x i64> <i64 63, i64 poison, i64 63>, [[X:%.*]]
+; CHECK-NEXT: [[R:%.*]] = shl nuw <3 x i64> <i64 1, i64 poison, i64 1>, [[S]]
; CHECK-NEXT: ret <3 x i64> [[R]]
;
- %s = sub <3 x i64> <i64 63, i64 undef, i64 63>, %x
- %r = shl <3 x i64> <i64 1, i64 undef, i64 1>, %s
+ %s = sub <3 x i64> <i64 63, i64 poison, i64 63>, %x
+ %r = shl <3 x i64> <i64 1, i64 poison, i64 1>, %s
ret <3 x i64> %r
}
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