[PATCH] D140602: [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative

[Anton Sidorenko via Phabricator via llvm-commits]

asi-sc added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/machine-combiner.ll:743
+  %t0 = call nsz reassoc half @llvm.minnum.f16(half %a0, half %a1)
+  %t1 = call nsz reassoc half @llvm.minnum.f16(half %t0, half %a2)
+  %t2 = call nsz reassoc half @llvm.minnum.f16(half %t1, half %a3)
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I believe we can remove nsz and reassoc flags here as well.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140602/new/

https://reviews.llvm.org/D140602