[PATCH] D140283: [RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine.

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:132
   // riscv-v-vector-bits-max should be no less than it.
-  if (RVVVectorBitsMax < (int)ZvlLen)
+  if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
     report_fatal_error("riscv-v-vector-bits-max specified is lower "
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Maybe add comment that 0 is default value when `-riscv-v-vector-bits-max` is not set.

To be very paranoid, do we need check if user is specifying max to `-2`, which the option's datatype does allow?


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Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:159
+  Key += "RVVMin";
+  Key += std::to_string(RVVBitsMin);
+  Key += "RVVMax";
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Maybe leverage Twine here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140283/new/

https://reviews.llvm.org/D140283