[PATCH] D140053: [RISCV] Add support for predication AND/OR/XOR/ADD/SUB with short-forward-branch-opt.
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 16 11:58:49 PST 2022
reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.
LGTM w/minor comment.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1066
+/// return the defining instruction.
+static MachineInstr *canFoldIntoCCMOV(Register Reg,
+ const MachineRegisterInfo &MRI,
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Can you rename this into something like canFoldIntoPredicateOp? CCMOV doesn't seem to be quite right here.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D140053/new/
https://reviews.llvm.org/D140053
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