[PATCH] D140053: [RISCV] Add support for predication AND/OR/XOR/ADD/SUB with short-forward-branch-opt.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 16 22:36:02 PST 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1066
+/// return the defining instruction.
+static MachineInstr *canFoldIntoCCMOV(Register Reg,
+                                      const MachineRegisterInfo &MRI,
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reames wrote:
> Can you rename this into something like canFoldIntoPredicateOp?  CCMOV doesn't seem to be quite right here.  
Sure. I took the name from ARM I think. Though theirs is MOVCC. I think their "Into" was kind of like "can fold with MOVCC."


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140053/new/

https://reviews.llvm.org/D140053



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