[PATCH] D140053: [RISCV] Add support for predication AND/OR/XOR/ADD/SUB with short-forward-branch-opt.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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sifive-7-series can predicate ALU instructions in the shadow of a
branch not just move instruction instructions.

This patch implements analyzeSelect/optimizeSelect to predicate
these operations. This is based on ARM's implementation.

I've restricted it to just the instructions we have test cases for,
but it can be extended in the future.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140053

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/select-binop-identity.ll
  llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

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