[PATCH] D139609: [AArch64][DAGCombiner] fold instruction BIC from ISD::AND

Tue Dec 13 22:32:22 PST 2022

bcl5980 added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/logical-op-with-not.ll:39-40
   %3 = and i32 %0, 65280
   %4 = xor i32 %3, -1
   %5 = and i32 %4, %1
   ret i32 %5
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mingmingl wrote:
> Related with scalar BIC DAG node (probably not a part of this patch)
> ```
> %4 = xor i32 %3, -1
> %5 = and i32 %4, %1
> ```
> itself could be a `BIC` as well.
> 
> `llc` with `-debug` shows `xor %3, -1` is combined into `or (xor %0, -1), -65281` so  [[ https://github.com/llvm/llvm-project/blob/9b35843e93ba5ced8749e076432bdbde36194458/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L2181 | tblgen pattern ]] won't see the `%4 %5` sequence.
Yeah, actually what this change do is reverting the `xor + or` to `xor + and`. 

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139609/new/

https://reviews.llvm.org/D139609