[PATCH] D139609: [AArch64][DAGCombiner] fold instruction BIC from ISD::AND

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16046
 
+// (~X | C) & Y --> bic Y, (X & ~C)
+static SDValue performAndCombineWithNotOp(SDNode *N, SelectionDAG &DAG) {
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mingmingl wrote:
> An alternative is `and Y, (orn C, X)`.
> 
> https://godbolt.org/z/PGnTdTMKW shows `orn` is generated if  RHS of `or` is not a constant or RHS is a large constant, but `orn` not generated for small constant.
> 
> https://gist.github.com/minglotus-6/dd2c75a2253b128081125a578e7ff6c6 is the llc ISel debug output for small constant, and https://gist.github.com/minglotus-6/2692d59e5c939941895d3581a4bdcbea for large constant.
> 
> I wonder if fixing ISel (after dag-combiner) is a more general solution (i.e., selects `~X | C` to `orn`, and fixes this motivating case as well).
> 
> 
> 
Yeah, we have two ways to fix the issue:
  and + orn
  and + bic
The problem for orn is it always need to involve a mov. So I choice and+bic to fix the issue.
I also try to add the code into ISelDAG, but it looks the code become complex and it will lose some optimization for the first `and`. Like the case @bic_shiftedreg_from_and.



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  https://reviews.llvm.org/D139609/new/

https://reviews.llvm.org/D139609