[PATCH] D139609: [AArch64][DAGCombiner] fold instruction BIC from ISD::AND

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16046
 
+// (~X | C) & Y --> bic Y, (X & ~C)
+static SDValue performAndCombineWithNotOp(SDNode *N, SelectionDAG &DAG) {
----------------
An alternative is `and Y, (orn C, X)`.

https://godbolt.org/z/PGnTdTMKW shows `orn` is generated if  RHS of `or` is not a constant or RHS is a large constant, but `orn` not generated for small constant.

https://gist.github.com/minglotus-6/dd2c75a2253b128081125a578e7ff6c6 is the llc ISel debug output for small constant, and https://gist.github.com/minglotus-6/2692d59e5c939941895d3581a4bdcbea for large constant.

I wonder if fixing ISel (after dag-combiner) is a more general solution (i.e., selects `~X | C` to `orn`, and fixes this motivating case as well).





================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16091
+
+  if (canGetNotFromOrXor(N, RHS)) {
+    if (X.getValueType() != VT)
----------------
nit: add a comment like `LHS won't be a constant sd node if RHS is not a constant, due to canonicalization`, or better assert the conditon.


================
Comment at: llvm/test/CodeGen/AArch64/logical-op-with-not.ll:39-40
   %3 = and i32 %0, 65280
   %4 = xor i32 %3, -1
   %5 = and i32 %4, %1
   ret i32 %5
----------------
Related with scalar BIC DAG node (probably not a part of this patch)
```
%4 = xor i32 %3, -1
%5 = and i32 %4, %1
```
itself could be a `BIC` as well.

`llc` with `-debug` shows `xor %3, -1` is combined into `or (xor %0, -1), -65281` so  [[ https://github.com/llvm/llvm-project/blob/9b35843e93ba5ced8749e076432bdbde36194458/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L2181 | tblgen pattern ]] won't see the `%4 %5` sequence.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139609/new/

https://reviews.llvm.org/D139609