[PATCH] D133379: [DL] Make vector ABI align bound by element align

Jannik Silvanus via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 9 02:53:13 PST 2022


jsilvanus added a comment.

In D133379#3971623 <https://reviews.llvm.org/D133379#3971623>, @beanz wrote:

> In D133379#3962893 <https://reviews.llvm.org/D133379#3962893>, @jsilvanus wrote:
>
>> How should this behave on overaligned element types? For example, with a `i16:32` data layout (as in the old DXIL data layout),
>> the second element in `<3 x i16>` will not be 32-bit aligned, even if the vector is.
>
> 16-bit types aren't supported with the old data layout at all. If you enable 16-bit types when compiling HLSL you get the new data layout which aligns 16-bit types to 16-bit boundaries. The only exception to that is some oddities around how buffers are packed, but that doesn't impact the data layout.

Sure -- but still the behavior on such cases should be clear, even if it is not relevant for DXIL. I just stumled over the formulation

> This alters the vector ABI alignment so that vector elements are always aligned appropriately for their type.

that is promising too much in this case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133379/new/

https://reviews.llvm.org/D133379



More information about the llvm-commits mailing list