[PATCH] D133379: [DL] Make vector ABI align bound by element align

Chris Bieneman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 5 11:10:38 PST 2022


beanz added a comment.

In D133379#3962893 <https://reviews.llvm.org/D133379#3962893>, @jsilvanus wrote:

> How should this behave on overaligned element types? For example, with a `i16:32` data layout (as in the old DXIL data layout),
> the second element in `<3 x i16>` will not be 32-bit aligned, even if the vector is.

16-bit types aren't supported with the old data layout at all. If you enable 16-bit types when compiling HLSL you get the new data layout which aligns 16-bit types to 16-bit boundaries. The only exception to that is some oddities around how buffers are packed, but that doesn't impact the data layout.

In D133379#3968986 <https://reviews.llvm.org/D133379#3968986>, @arsenm wrote:

> Can dxil vectors be translated as arrays instead? Feels like someone interpreted vectors as directly mapping to a language language rather than a feature that doesn’t fit its needs.

DXIL is a shipped binary interface using IR vectors in this way. The current compiler does this without capturing the behavior in the data layout, which is something we'd like to change as we upstream the work.

In D133379#3968993 <https://reviews.llvm.org/D133379#3968993>, @arsenm wrote:

> I have wanted to allow preferred alignments to be lower than the ABI alignments. Can we get per-type alignment specification instead of a global modifier?

Per-type specification makes sense, I can update the patch later this week.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D133379



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