[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:14
+// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max).
+// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base)
+// configurations have essentially same scheduling characteristics.
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`SCR1_CFG_RV32EC_MIN (scr1-min)` -- this should be removed from comment as well since patch doesn't cover `scr1-min`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302