[PATCH] D139442: AMDGPU/MC: Make VReg and VISrc decoders more strict

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added a comment.

> In most cases if instruction can't use some bits in encoding of an operand, those bits are set to default value in td file.

AFAIK, we use `?` as a default value to allow disassembler ignore these bits.

> Another option would be to make new OperandType and write some error msg in InstPrinter (I would print normal src operand + msg that operand value is invalid and reason why(e.g. not vgpr/not vgpr or inline imm)).

I think that would be perfect!


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  https://reviews.llvm.org/D139442/new/

https://reviews.llvm.org/D139442