[PATCH] D139442: AMDGPU/MC: Make VReg and VISrc decoders more strict

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

In most cases if instruction can't use some bits in encoding of an operand, those bits are set to default value in td file. Disassembler fails (in generic way) in this cases and does not print e.g. "instruction must use glc" (assembler prints such verbose warnings)

This is the corner case where some combinations of bits in the operand encoding are not allowed. Those cases are too complicated to be implemented in tablegen encoding so I moved it to decoder.

> Would it be possible to modify your patch and decode invalid operands with a comment stating that they are incorrect?

I don't know where would be the best place to implement it, but as far I am aware it is not done for any other instruction.
Maybe return errOperand instead of MCOperand() but it does not seem to make any difference.
Another option would be to make new OperandType and write some error msg in InstPrinter (I would print normal src operand + msg that operand value is invalid and reason why(e.g. not vgpr/not vgpr or inline imm)).


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https://reviews.llvm.org/D139442